1. Field of the Invention
This invention relates to an apparatus, method and system for translation lookaside buffer (“TLB”) coherence in computer systems; more particularly, this invention relates to an apparatus, method and system for TLB coherence in multi-processor computer systems.
2. The Related Art
Virtual memory systems allow the addressing of large amounts of memory as though all of that memory were the main memory of the computer system even though actual main memory may consist of a substantially lessor amount of storage space. Virtual memory systems accomplish this by providing memory management units which translate virtual memory addresses into physical memory addresses. The physical addresses may be stored in the main computer memory, in cache memory systems, or otherwise.
If the physical address is kept in the main computer memory, the main computer memory uses lookup tables to locate the physical address. The computer compares the virtual address to the values stored in the tables to determine the physical address. There are often several levels of tables, and the comparison takes a long time to locate. To overcome this delay, the physical address may be stored in cache memories. Cache memories are fast components to store recently used data and instructions. The caches are first looked at by a processor before going to main memory for any information and are therefore usually connected so that they are rapidly accessible to the processors.
However, the cache memories must be addressed to obtain the information they contain. If addressed using physical addresses, then address translation is required from the virtual address to the physical address. To accomplish this without the use of lookup tables, a typical memory management unit uses a TLB to cache virtual page addresses that have been recently accessed along with their related physical page addresses.
When the TLB is provided with a virtual address that it has, it will provide the corresponding physical address. The physical address, if in the cache memory, allows for immediate access to information that is available to the processor without having to access the page lookup tables in the main memory. If the virtual address is not located in the TLB, otherwise known as a “TLB Miss,” the physical address must be retrieved from the lookup tables in the main computer memory system. When the physical address is recovered, it is then stored along with other virtual addresses in the TLB so that it will be immediately accessible the next time. When the information is recovered, it is then stored in the cache under the physical address for immediate access.
Without the TLB, each memory access, either read or write, involved the main computer memory system. Typically the main computer memory system was distantly located, and also was relatively slow in operation. It was found that storing and mapping the addresses in a TLB would be more efficient since it was closer to the processor and faster and reading and writing the data than the main computer memory system. In a multiple processor system that has a TLB associated with each processor, each TLB may contain data associated with a main computer memory system, and each processor may process the data for the addresses and store the results in its respective TLB. Thus, it is possible that many different data values will exist among the multiple TLBs for a single address. This possible inconsistency among corresponding address locations is referred to in the art as the TLB coherency problem.
For a computer system with one processor, the time to provide TLB coherence is not time consuming. The operating system manages TLB coherence to both reference the physical address and/or to remove mappings entered to all the TLBs. However, it is time consuming to provide TLB coherence in multi-processor computer systems. Currently, the operating system sends messages to each individual processor. Each processor is then required to take a trap to the operating system to remove or enter the data into its respective TLB.
There are several disadvantages to the current TLB coherence method. First, it is expensive to provide a trap for each individual processor. Second, the process is very time consuming and slow. Lastly, the process disrupts the executing process of the system and results in future delay. Thus, there exists a need for a more efficient and quicker TLB coherence method for multi-processor systems.